The present invention generally relates to information handling and data processing systems, processors, and more specifically to recovering and restoring Logical Registers after a flush operation.
Modern information and data handling systems often execute instructions out of order to achieve greater processing efficiency. To handle executing out-of-order instructions, processors typically are “pipelined” and have multiple elements that operate in parallel to process multiple instructions in a single processing cycle. Pipelining involves processing instructions in stages, so that the pipelined stages may process a number of instructions concurrently. To improve throughput, processors may include multiple pipelines or execution slices within each processor core. Multiple execution slices may be used as part of simultaneous multi-threading within a processor core.
Typically, a processor pipeline may refer to a set of data processing circuitry or hardware units arranged in series within a processor. The processor pipeline usually includes a number of stages, and may include an “instruction fetch” stage where an instruction is fetched from memory. In a “decode” stage, the instruction is decoded into different control bits, which in general designate (i) a type of functional unit (e.g., execution unit) for performing the operation specified by the instruction, (ii) source operands for the operation, and (iii) destinations for results of the operation. In a “dispatch” stage, the decoded instruction is dispatched to an issue queue (ISQ) where instructions wait for data and an available execution unit. Next, an instruction in the issue queue (ISQ) typically is issued to an execution unit in an “execution” stage. The “execution” stage processes the operation as specified by the instruction. Executing an operation specified by an instruction typically includes accepting data, e.g., one or more operands, and producing one or more results. There are usually registers and queues associated with the execution units and/or the issue queue (ISQ) to hold data, information and/or instructions for the execution units.
An out of order processor typically executes instructions as soon as its operands are available (and valid), independent of the original instruction sequence. Consequently, as these processors execute out-of-order instructions, they generate numerous temporary register results. The temporary values are stored together with completed values in register files. The temporary values become complete or permanent values when the corresponding instructions are complete.
Executing instructions out-of-order creates additional complexity in handling and processing instructions. Depending upon how the instructions are handled in out-of-order processors, processor latency and inefficiency may result. In out-of-order processors, an instruction can change a register value before all of the prior instructions complete. If any of the prior instructions cause an exception or interruption, then all of the sequential instructions prior to the time of the exception, e.g., an interruptible instruction, will need to be flushed. As a result, the registers allocated to the instructions being flushed will also need to be flushed.
One of the complexities in handling and processing out-of-order instructions is restoring the processor state in the event of an interruptible instruction, e.g., a mispredicted branch instruction. In this regard, logical registers will need to be restored to the state they were in before the exception, e.g., interruptible instruction. For this reason, out-of-order processors typically have a history buffer, e.g., Save & Restore Buffer (SRB), that stores the content of logical registers in order to recover the content of the logical registers in the event of an exception. If an exception occurs, for example, a branch mispredict, then typically the content of the logical registers is flushed, and data is recovered from the history buffer, e.g., SRB, to place the logical registers in the condition that existed before the exception, e.g. the interruptible instruction. Flushing and recovering the contents of the logical registers can introduce latency and delay to a processor.